The present invention relates to a semiconductor integrated circuit (hereinafter referred to as an IC) in which a protocol decoding function and a micro-controller function, which are used for a serial data receiving device typified by a wireless call device (hereinafter referred to as a pager), are integrated.
Also, the present invention relates to an IC having a communication protocol decoding function used for a serial data receiving device typified by a pager or the like.
Further, the present invention relates to an IC having a protocol decoding function used for a serial data receiving device typified by a pager or the like and a method of saving a battery thereof.
A portable serial data receiving device, used as a pager or the like, having a block structure as shown in FIG. 2 is conventionally used. This receiving device includes a system clock generating circuit 4 for generating timing signals on receiving an output of an oscillating circuit 1, a data receiving circuit 3 for synchronously making entry of data inputted through a serial data input terminal C on receiving the clock output, and for checking an ID and detecting and correcting an error for the entered data, that is, the data receiving circuit having a so-called protocol decoding function, and a micro-controller circuit 69 for controlling the data receiving circuit 3 on receiving the clock from the system clock generating circuit 4, for making entry of the received data to process the data, and at the same time, for informing the outside of the reception.
A resonator (normally crystal resonator) is connected between input and output terminals A and B of the oscillating circuit 1. The oscillation output is used as a reference clock for synchronization of the data receiving circuit 3 and for operating a processing circuit. Also, the oscillation output is inputted into the system clock generating circuit 4 and is converted into a system clock necessary for the operation of the micro-controller circuit 69.
A pager as an example will be described. In FIG. 2, data inputted through the data input terminal C is entered in the data receiving circuit 3. At that time, synchronization is made by using the output of the oscillating circuit 1. When the data receiving circuit 3 confirms the data reception by checking the ID, it requests interruption of the micro-controller circuit 69, and starts to make entry of the data. The entered data is entered into the micro-controller circuit 69 which has started its operation by receiving the interruption request, and is stored or displayed as occasion demands. The micro-controller circuit 69 is also provided with an output terminal D through which an alarm sound is given to the outside at the data reception or an LED is turned on, so that it outputs an alarm signal as occasion demands.
In this way, data processing is executed. However, in the structure shown in FIG. 2, since the output of the oscillating circuit 1 is connected to both the data receiving circuit 3 and the system clock generating circuit 4, as a data rate becomes fast, a processing time of the micro-controller is required to be shortened.
FIG. 3 shows another prior art in which two oscillating circuits are included. The respective outputs of oscillating circuits 1 and 67 are inputted into a clock switching circuit 68. The clock switching circuit 68 is controlled by a control signal G of the micro-controller circuit 69, and the output thereof is inputted into the system clock generating circuit 4. Since other components are common to those of the example shown in FIG. 2, they are designated by similar reference numerals or symbols and the description thereof will be omitted. In the circuit shown in FIG. 3, in the case where a processing speed of the micro-controller circuit 69 is insufficient, the oscillating frequency of the oscillating circuit 67 is increased and a clock is changed as occasion demands, so that the speed of the system clock can be increased.
Also, a portable serial data receiving device, used as a pager or the like, having a block structure as shown in FIG. 9 is conventionally used. The receiving device includes a frequency dividing circuit 2 for dividing the output of a reference clock generating circuit 17; a control circuit 18 for generating a control signal on receiving the output of the circuit 2; a synchronization correcting circuit 5 connected to a data input terminal C and operating with the receipt of a clock from the frequency dividing circuit 2; an error correcting circuit 6, a signal detecting circuit 7 and a synchronization code detecting circuit 8 which are operated by receiving the output of the circuit 5 and the outputs of the frequency dividing circuit 2 and the control circuit 18; an address comparing circuit 9 receiving the output of the frequency dividing circuit 2 and the control circuit 18 and checking the outputs of the error correcting circuit 6 and an address memory circuit 10; and an input/output control circuit 11 connected to the address memory circuit 10, receiving the outputs of the control circuit 18 and the error correcting circuit 6, and connected to an input/output terminal 12. In FIG. 9, all components other than the reference clock generating circuit 17 and the frequency dividing circuit 2 will be collectively referred to as a data receiving circuit 3.
FIGS. 10 and 11 show a conventional structure of the address memory circuit 10 in FIG. 9. FIG. 10 shows an example of the conventional address memory circuit formed by using a shift register. When one address is composed of n bits, it is stored in the shift register in the drawing. Since a plurality of addresses are generally assigned to a receiving device, a plurality of register each shown in the drawing are actually provided. In this case, an input 30 is selected by a switching circuit, and address data is written synchronously with a clock 20. The output is also selected by the switching circuit and inputted into the address comparing circuit. When n is a small value, outputs 331 to 30+n in the drawing are simultaneously compared with each other, and comparison is sequentially made by switching for every address register. On the other hand, when n is a large value, a terminal corresponding to 31 in the drawing is first selected for all address registers, and the output is inputted into the address comparing circuit. Next, terminals are sequentially switched to 32, 33, and the outputs till 30+n are inputted into the address comparing circuit. The sequence of selection may be opposite to this.
FIG. 11 shows an example of the conventional address memory circuit formed by using latches. In the drawing, a latch is written and read through an 8-bit bus line. In the drawing, the number of bits of the address is 18, and an enable bit of the address is added thereto. The output of the address memory circuit is inputted, as Q(0:18), into the address comparing circuit.
As described above, since a plurality of addresses are normally used, a plurality of circuits each shown in the drawing are used and switched by a selector to input an address into the address comparing circuit. The sequence of switching is executed for each address as described before or executed for each of the same bit for a plurality of addresses.
As a protocol decoding IC for communication used for a pager or the like, one shown in FIG. 13 is conventionally used. In the drawing, a signal inputted through an input terminal C is processed by a decoding means 50, and is outputted as data. This decoding process is referred to as protocol decoding. In this prior art, the decoding means 50 includes a synchronization correcting circuit 5, and an error correcting circuit 6, a signal detecting circuit 7, and a synchronization code detecting circuit 8 which receive the output of the circuit 5. The output of the decoding means 50 is inputted into an informing means 51 and a control means 19. The informing means 51 is connected to a memory 60 which stores a number of its self, and when coincidence of the number and the receiving data is detected, it is informed. On the other hand, the control means 19 outputs a timing signal to the outside. The timing signal is used to make a receiving device execute an intermittent operation, and is referred to as a battery saving signal. The signal received by the receiving device is demodulated and detected, and is inputted into the input terminal C.
FIG. 14 shows timing of an intermittent operation for a POCSAG system as an example. In the drawing, FIG. 14(a) shows a transmission signal of the POCSAG. Repetitive pattern of 1, 0, 1, 0, . . . referred to as a preamble is first transmitted, and subsequently, a synchronous code (SC) is transmitted. At the fixed timing (timing of self frame) between the synchronous code and the next synchronous code, an address (ADR) as the number of a self station and a message (M) subsequent thereto are transmitted.
FIG. 14(1) shows a battery saving signal which is conventionally known. In the drawing, when the signal level is xe2x80x9cHxe2x80x9d, a receiving device operates. First, when the preamble signal is detected, the receiving device continues to receive until the synchronous code is detected, and after the synchronous code is detected, the self frame and the synchronous code are alternately received. Then, when the self address is found in the self frame, the message is sequentially received.
FIGS. 14(2) and 14(3) show signal waveforms based on a battery saving method disclosed in Japanese Patent Unexamined Publication No. Sho 63-13432. In FIG. 14(2), after the synchronous code is once detected, synchronization detection is executed by only the self frame. In FIG. 14(3), after the synchronous code is once detected, synchronization detection is carried out by only self frame, and reception for detecting the preamble is carried out also at the timing of the synchronous code.
However, in the conventional serial data receiving device as shown in FIG. 2, it is impossible to increase an oscillation frequency to shorten a processing time of the micro-controller. Because the reference clock is changed according to this, and the clock of the data receiving circuit is also changed, so that the timing signal of the data receiving circuit is changed. Accordingly, the oscillation frequency is selected in accordance with the data receiving circuit. As a result, there arises a problem that a processing speed of the micro-controller may be insufficient.
In the serial data receiving device shown in FIG. 3, in order to shorten the processing time of the micro-controller, it is necessary to provide a separate oscillating circuit to switch a clock, so that there are problems that consumed electric power is increased, and at the same time, software becomes complicated, which causes disadvantage in cost.
In the conventional serial data receiving device shown in FIGS. 9 to 11, there is a problem that when the number of received addresses increases, the increase of a circuit scale becomes remarkable. For example, in the pager, according to the increase and diversification of services, the number of necessary addresses increases in recent years. Thus, the circuit scale of an IC necessary for the receiving device also tends to increase. Particularly, a memory circuit of address comes to occupy a large part of the IC.
Accordingly, there has been a problem to lessen the area of an address memory circuit occupying an IC without deteriorating the functional quality.
The conventional receiving method as shown in FIG. 14 has had a problem described below. First, as for FIG. 14(1), consumed electric power becomes large since a synchronous code is detected each time. Since almost all power consumption of a pager is made at a receiving portion, it is important to decrease an operation time of the receiving device even if only slightly.
One of objects of FIGS. 14(2) and 14(3) is to deal with such a problem. In this case, in FIGS. 14(2) and 14(3), the operation of synchronization depends on the address of a self frame. That is, by the coincidence of address of the self frame, synchronization is confirmed. In this case, if there is a base station for transmitting messages as the need arises while the synchronous stated is always maintained by synchronous codes after a preamble is first transmitted, there is a possibility that synchronization becomes impossible to be maintained.
In view of these problems of the prior art, an object of the present invention is to provide a semiconductor integrated circuit for communication which is able to deal with a base station executing transmission while always maintaining synchronization, and to improve the efficiency of battery saving in a waiting state.
In the present invention, in order to solve these problems of the prior art, the output of an oscillating circuit is supplied to a data receiving circuit through a frequency dividing circuit, while the oscillating circuit output is directly supplied to a system clock generating circuit of a micro-controller. The oscillation frequency of the oscillating circuit is made X times higher, and the dividing ratio of the frequency dividing circuit is made 1/X.
Also, in the present invention, in order to solve these problems of the prior art, as another solving means, the output of a reference clock generating source is directly supplied to a data receiving circuit while being supplied to a system clock generating circuit of a micro-controller through a frequency multiplying circuit. The multiplying ratio of the multiplying circuit is made Y.
In a serial data receiving device using the thus constructed semiconductor integrated circuit for communication, even in the case where a data rate of communication is made high and the increase of processing speed of the micro-controller is required, it is possible to make the processing speed of the micro-controller X times higher and Y times higher, respectively.
Further, in the present invention, in order to solve these problems of the prior art, an address memory circuit is formed of a dual port RAM.
The area of the thus constructed address memory circuit on an IC becomes remarkably small as compared with a conventional case using a shift register or latch. On the other hand, since reading of data can be carried out at the similar timing to the conventional case where the shift register or latch is used, the same function can be realized using the same clock of the conventional case.
Further, in the present invention, in order to solve these problems, a memory means is added to a conventional decoding means, so that when a synchronous code is detected, it is stored, and the receiving device is stopped at a next synchronous code. Then, synchronization is again confirmed at a further next synchronous code. On the contrary, even in the case where the synchronous code is not detected, it is stored and the reception is executed at the timing of an immediately next synchronous code.